{"id":2816,"date":"2022-11-06T16:18:10","date_gmt":"2022-11-06T21:18:10","guid":{"rendered":"https:\/\/www.hajim.rochester.edu\/ece\/sites\/laics\/?page_id=2816"},"modified":"2022-11-06T20:58:28","modified_gmt":"2022-11-07T01:58:28","slug":"hp_cg_d","status":"publish","type":"page","link":"https:\/\/www.hajim.rochester.edu\/ece\/sites\/laics\/hp_cg_d\/","title":{"rendered":"High-Performance Clock Generation and Distribution"},"content":{"rendered":"

Energy-Efficient RF and High-Speed Integrated Circuits<\/h3>\n

As both the data rate and system complexity of communications and computing increase, power consumption becomes increasingly critical, particularly in high-performance microprocessors, mobile wireless communications, and sensor applications. While advances in semiconductor materials and devices can change the fundamental limits on the power consumption such as gate leakage, new circuit techniques are needed to approach these limits, and more importantly, to enable the use of low-cost main-stream process technologies such as CMOS to achieve high power efficiency. In this research thrust, we explore new circuit technologies to significantly lower the power consumption of some critical building blocks in RF systems and high-speed digital VLSIs. Our approach is to leverage the nonlinear characteristics of active devices, and control the power spectrum of signals, in addition to conventional RF techniques such as power matching. In particular, we are pursuing a circuit technique,\u00a0injection locking<\/em>. Current projects include injection-locked oscillators (ILO) and\u00a0injection-locked frequency dividers (ILFD)<\/a><\/span>.<\/p>\n

\"\"<\/p>\n

18GHz Divide-by-3 Injection-Locked Frequency Divider<\/strong>
\nApplication: PLL, frequency synthesizer, radar
\nInnovation: differential mixing, harmonic processing
\nTechnology: 0.18um standard digital CMOS
\nLocking range: 6%, 19% extended
\nPower dissipation: 4.6mW
\nPhase noise: 9dB down from input (ideal)<\/p>\n

\"\"<\/p>\n

19GHz Divide-by-2 Injection-Locked Frequency Divider<\/a>
\nApplication: PLL, frequency synthesizer, radar
\nInnovation: shunt-peaking locking-range enhancement
\nTechnology: 0.35um CMOS
\nLocking range: 17%
\nPower consumption: 1mW
\nPhase noise: 6dB down from input (ideal)<\/p>\n","protected":false},"excerpt":{"rendered":"

Energy-Efficient RF and High-Speed Integrated Circuits As both the data rate and system complexity of communications and computing increase, power consumption becomes increasingly critical, particularly in high-performance microprocessors, mobile wireless…<\/p>\n","protected":false},"author":36,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-2816","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nHigh-Performance Clock Generation and Distribution - Laboratory for Advanced Integrated Circuits and Systems<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.hajim.rochester.edu\/ece\/sites\/laics\/hp_cg_d\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"High-Performance Clock Generation and Distribution - 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