{"id":154992,"date":"2024-04-23T15:54:44","date_gmt":"2024-04-23T19:54:44","guid":{"rendered":"https:\/\/www.hajim.rochester.edu\/senior-design-day\/?p=154992"},"modified":"2025-05-02T14:53:16","modified_gmt":"2025-05-02T18:53:16","slug":"measuring-data-access-latency-in-large-cpu-caches","status":"publish","type":"post","link":"https:\/\/www.hajim.rochester.edu\/senior-design-day\/measuring-data-access-latency-in-large-cpu-caches\/","title":{"rendered":"Measuring Data Access Latency in Large CPU Caches"},"content":{"rendered":"\r\n<h2 class=\"wp-block-heading\">Author<\/h2>\r\n\r\n\r\n\r\n<p>Shaotong Sun<\/p>\r\n\r\n\r\n\r\n<h2 class=\"wp-block-heading\">Mentors<\/h2>\r\n\r\n\r\n\r\n<p>Chen Ding and Michael Scott<\/p>\r\n\r\n\r\n\r\n<h2 class=\"wp-block-heading\">Abstract<\/h2>\r\n<p>This practitioner paper describes a new, multi-locality benchmark program for testing memory access latency and using it to study recent AMD machines equipped with 3D vertical cache(V-Cache) that can be over 1 GiB in total size on a single node. The latency study shows that these large caches differ from traditional LLCs in two aspects: the V-Cache is partitioned rather than shared, and the cache replacement policy is more similar to random than it is to LRU.<\/p>\r\n<p><a href=\"https:\/\/www.hajim.rochester.edu\/senior-design-day\/wp-content\/uploads\/2024\/04\/Poster-SHAOTONG-SUN-1.pdf\">Measuring Data Access Latency in Large CPU Caches<\/a><\/p>\r\n","protected":false},"excerpt":{"rendered":"<p>This practitioner paper describes a new, multi-locality benchmark program for testing memory access latency and using it to study recent AMD machines equipped with 3D vertical cache(V-Cache) that can be over 1 GiB in total size on a single node.<\/p>\n","protected":false},"author":6242,"featured_media":160422,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_coblocks_attr":"","_coblocks_dimensions":"","_coblocks_responsive_height":"","_coblocks_accordion_ie_support":"","_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"categories":[4442,96],"tags":[],"coauthors":[8612],"class_list":["post-154992","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-archive","category-csc-archive"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.3 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Measuring Data Access Latency in Large CPU Caches - Senior Design Day<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.hajim.rochester.edu\/senior-design-day\/measuring-data-access-latency-in-large-cpu-caches\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Measuring Data Access Latency in Large CPU Caches - Senior Design Day\" \/>\n<meta property=\"og:description\" content=\"This practitioner paper describes a new, multi-locality benchmark program for testing memory access latency and using it to study recent AMD machines equipped with 3D vertical cache(V-Cache) that can be over 1 GiB in total size on a single node.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.hajim.rochester.edu\/senior-design-day\/measuring-data-access-latency-in-large-cpu-caches\/\" \/>\n<meta property=\"og:site_name\" content=\"Senior Design Day\" \/>\n<meta property=\"article:published_time\" content=\"2024-04-23T19:54:44+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2025-05-02T18:53:16+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.hajim.rochester.edu\/senior-design-day\/wp-content\/uploads\/2024\/04\/Screen-Shot-2024-04-23-at-3.52.39-PM.png\" \/>\n\t<meta property=\"og:image:width\" content=\"394\" \/>\n\t<meta property=\"og:image:height\" content=\"252\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"admin\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"admin\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/measuring-data-access-latency-in-large-cpu-caches\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/measuring-data-access-latency-in-large-cpu-caches\\\/\"},\"author\":{\"name\":\"admin\",\"@id\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/#\\\/schema\\\/person\\\/351018fbcf84ed8cac6d8072ba5b347c\"},\"headline\":\"Measuring Data Access Latency in Large CPU Caches\",\"datePublished\":\"2024-04-23T19:54:44+00:00\",\"dateModified\":\"2025-05-02T18:53:16+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/measuring-data-access-latency-in-large-cpu-caches\\\/\"},\"wordCount\":103,\"image\":{\"@id\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/measuring-data-access-latency-in-large-cpu-caches\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.hajim.rochester.edu\\\/senior-design-day\\\/wp-content\\\/uploads\\\/2024\\\/04\\\/Screen-Shot-2024-04-23-at-3.52.39-PM.png\",\"articleSection\":[\"3. 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