Professor of Electrical and Computer Engineering
Professor of Computer Science
PhD, University of Illinois at Urbana-Champaign, 2002
414 Computer Studies Building
Michael Huang received the BS degree in computer science and engineering from Tsinghua University, Beijing, in 1994, the MS and the PhD degree in computer science from University of Illinois at Urbana-Champaign in 1999 and 2002, respectively. From 1994 to 1997, he was a lead architect in building a 32-processor hierarchical shared-memory multiprocessor research prototype. He joined the faculty of the Electrical and Computer Engineering department in 2002. In 2010, he was at IBM T. J. Watson Research Center working on future POWER processor concept development.
His research interests include various aspects of high-performance computer architecture such as processor microarchitecture, communication and memory substrate, reliability, and energy-efficient and complexity-effective design. He is particularly interested in addressing emerging issues and exploring co-design of device, circuit, and systems. He is a recipient of the NSF CAREER award, an IBM Faculty Award, a member of the “Hall of Fame” of ISCA and HPCA, and a member of the IEEE and the ACM.
Increasing reliance on computing as a means of scientific exploration demands ever higher speed, reliability, and efficiency from high-performance systems. Achieving sustained gain in all these metrics requires continued innovation in processor microarchitecture, the communication and coherency substrate, and the underlying device technology. Such innovation builds upon concrete understanding of the interaction of these components. Our research spans these components and focuses on delivering practical, complexity-effective solutions. In addition to architectural exploration, we are also investigating how to leverage new technologies and circuit techniques. For example, we are investigating the use of optics as well as mixed-signal circuits to design nature-based non-von Neumann computings systems known as Ising machines.
Representative recent publications: (full list)
ISCA’22: “Increasing Ising Machine Capacity with Multi-Chip Architectures”, Anshujit Sharma, Richard Afoakwa, Zeljko Ignjatovic, and Michael Huang, in Proc. of the 49th Int’l Symposium on Computer Architecture, June 2022
HPCA’21: “BRIM: Bistable Resistively-Coupled Ising Machine”, Richard Afoakwa, Yiqiao Zhang, Uday Kumar Reddy Vengalam, Zeljko Ignjatovic, and Michael Huang, in Proc. of the 27th Int’l Symposium on High-Performance Computer Architecture, Feb. 2021
ASPLOS’19: “Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance”, S. Kondguli and M. Huang, in Proc. of the 24th Int’l Conf. on Architectural Support for Programming Languages and Operating Systems, April 2019