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Electrical and Computer Engineering Colloquia Series

 

Memory Technology: what every researcher should know

J. Thomas Pawlowski

Wednesday, November 28, 2018
Noon–1 p.m.
1400 Wegmans Hall

During the “easy” years of CMOS technology scaling in which we could count on a doubling of transistor count every two years and an increase in transistor performance, the role of the processor or memory architect was to best direct how to take advantage of these ever improving capabilities. But Denard scaling came to an end around 2004. Technology scaling of anything using CMOS  slowed in every manner of foundry, whether digital or analog or memory which we first observed  around 2013 and now appears plain to even the last of the Moore’s Law disciples. Thus an exciting new era is upon us driven by the new technology scaling reality. Yet the relentless drive for more performance and more intelligence in silicon continue unabated. The role of everyone in the silicon production ecosystem has now been forced to evolve into an even more exciting one as we seek more creative solutions so that the forward march of delivered capabilities continues. More than ever, we turn to improvements in memory itself and in the manner of processor-memory interactions for solutions. In this talk we will discuss the numerous memory technologies that are available and also upcoming emerging technologies as well as different architectures deployed. We will examine their scaling past and future. We will investigate the potential for new ways in which processors and memory may interact. And perhaps most importantly, we will encourage the research community’s directions for exploration and discourage areas which will be unfruitful.  This will be a highly interactive presentation and you are encouraged to bring your toughest questions and problems for discussion.

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Thomas Pawlowski is a Fellow and Chief Technologist with Micron’s Advanced Computing Solutions Group. His responsibilities include advising on new technologies, investments, system architectures and memory product/subsystem architectures.

For the past twenty-six years at Micron, Mr. Pawlowski has had the pleasure of making key technical contributions to many new memory and system architectures such as synchronous burst pipelined SRAM; ZBT SRAM; DDR and QDR SRAM, PSRAM; high-speed NAND; multi-channel memory; DDR DRAM; RLDRAM; 3D memory; LPDRAM, HBM, Micron Automata Processor; abstraction protocols; new ECC concepts; processing near memory concepts and others yet to be announced. His current projects include 3DXpoint system architecture, emerging memory architectures, and further advances in future high-performance DRAM. Mr. Pawlowski serves on numerous conference committees and advisory boards. He has been keynote speaker at many conferences such as MemSys, MICRO, IPDPS and others. He has served as chair of several JEDEC committees including SRAM, Flash, and was the founding father and chair of the low power memory committee for DRAM and Flash.

Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada and has over 150 U.S. patents granted and in-progress. He was named an IEEE Fellow for his contributions to memory.

 

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