VLSI Complexity Single Flux Quantum Systems

Tahereh Jabbari

Supervised by Eby Friedman

703 Computer Studies Building

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Superconductive electronics and, specifically, single flux quantum (SFQ) circuits are attracting significant attention as a promising ultra-low power and ultra-high speed circuit technology for beyond CMOS exascale supercomputing. Superconductive electronics is suitable for large scale, energy efficient, stationary cloud computing, “big data” applications, and ultra-high speed neural networks. Significant development in the design and manufacture of superconductive electronics for prospective exascale computing systems has led to device densities exceeding 4.2×10⁶ Josephson junctions (JJs) per cm² – sufficient to enable large scale SFQ systems. The lack of electronic design automation (EDA) tools, however, is currently a serious issue affecting the development of complex SFQ circuits. Advances in EDA algorithms and design and analysis methodologies and techniques are therefore required to enhance the development of VLSI complexity SFQ systems.

In this dissertation, issues and solutions to enable, connect, and secure VLSI complexity SFQ system are presented. Topics such as interconnects, ultra-high speedclocking and synchronization, signal interfaces, and deep scaling of superconductive structures are described, and related design methodologies, algorithms, circuits, and expressions are proposed.

On-chip signal routing has become an issue of growing importance in modern VLSI complexity SFQ systems. Specialized routing methods for these systems are presented. The routing methods include passive transmission lines as global interconnect and Josephson transmission lines as local interconnect. Guidelines are provided for determining when to use global and local interconnects. Novel methodologies, algorithms, and expressions have been developed to manage resonance, flux trapping, and coupling in VLSI complexity SFQ circuits. The design of an SFQ clock distribution network is a challenging problem due to timing uncertainties at very high frequencies, gate-level pipelining, and fanout constraints. Near zero skew clock tree targeting large scale SFQ circuits is proposed to improve the global timing process while eliminating skew uncertainty. To enable higher fanout, area efficient splitter topologies are developed, producing a clock network suitable for large scale SFQ systems. All-JJ superconductive circuits based on bistable superconductor-ferromagnet-superconductor are presented to enable nanometer feature sizes for VLSI superconductive systems. These specialized guidelines, algorithms, and circuits enable deep scaling of super- conductive systems for stationary high speed, ultra-low energy applications.