Ph.D. Public Defense

Scalable Spin Torque Driven Devices and Circuits for High Performance Memory and Computing

Mohammad Kazemi

Supervised by Professor Mark Bocko

Monday, April 8, 2019
2:30 p.m.

Computer Studies Building, Room 703

As CMOS technology approaches the intrinsic limits of scalability, higher performance requires more power consumption and circuit area. Employing the spin degree of freedom of electrons alone or in combination with the charge of electrons provides opportunities to reduce the power dissipation, enhance the performance of operation, and increase the integration density of computing systems. This dissertation describes studies of nanomagnetic spin-based devices and associated CMOS circuits for scalable, high performance memory and computing systems.

The power, speed, and area tradeoffs associated with the magnetoresistive random access memory (MRAM) operating on the spin-transfer torque (STT) mechanism are investigated. Then, a memory system is presented which effectively addresses the challenges associated with the STT-MRAM by providing a hybrid dynamic/nonvolatile platform for data retention. The focus is next turned to memory and logic devices operating on spin-orbit torques (SOTs). To pave the way toward very-large-scale-integration (VLSI) systems delivering high performance operation with low power dissipation, mechanisms are described to effectively address three fundamental challenges in spin-orbitronics: (a) All-electrical deterministic switching, (b) Intrinsic logic operation, and (c) scalability.

It is shown that shaping the magnetic energy landscape of perpendicular-anisotropy devices breaks the symmetry of the SOT operation on the magnetization, thus enabling all-electrical switching using unipolar current pulses. It is also shown that the capability to switch magnetic devices with unipolar current pulses leads to a spin-orbit MRAM cell which, in contrast to state-of-the-art cells, provides read/write access via a single transistor.

For spin-based computing to be adopted widely, energy efficient, high performance logic gates comprised of as few devices as possible are required. A universal logic gate is presented that can be implemented using the minimum possible number of spin-orbit devices. The gate performs logic operations in a ‘stateful’ manner, that is, the same devices retaining the logic operands simultaneously perform the logic operations and latch the outcome. Such universal logic gates greatly increase on-chip computational resources which can be effectively utilized thanks to the low energy dissipation.

Finally, it is shown that scalability is not a fundamental limitation in spin-orbitronics. Design rules are derived that indicate the path to building deeply scalable spin-orbit devices exhibiting sub-nanosecond switching time at room temperature. Accordingly, we show that the spin-orbitronics may serve as a universal memory technology capable of implementing multiple levels of memory hierarchy.