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Augmented Transactional Memory


Beakal Lemeneh


Michael L. Scott and Sandhya Dwarkadas


Multithreading introduces complications around synchronizing different threads with shared memory spaces. Lock-based synchronization, one of the ways used to synchronize multithreaded applications, introduces a performance penalty when threads wait to update a data protected by a lock. Transactional memory, a type of lock-free synchronization, is considered a promising alternative to different lock-based synchronization overhead in the absence of inter-thread conflicts. The conflict detection mechanism used in transactional memory to enforce correctness, isolation and atomicity, between conflicting threads is defined at the private cache level, which limits the practicality of transactional memory due to constant failures and reverting the changes made by a speculative region back to its initial state in the code when interference between threads is common in the application. Looking at prior implementations of non-speculative access in a speculative region in AMD’s ASF and prior experience using suspend/resume instructions in IBM’s Power Architecture to maintain adherence to sequential semantics between iterations in loops, it is our belief that enabling special non-speculative access in a speculative region by leveraging the semantics of the application could enhance the success rate of transactions in transactional memory and increase the computation speed of the application. This project focuses on 1) extending the RISCV ISA to incorporate hardware transactional memory on Gem5 and 2) introducing special nonspeculative load and store instructions to allow speculation to succeed in a significantly more comprehensive range of applications to improve the performance of different multithreaded applications.

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